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Ordering number : EN5914
CMOS IC
LC75396NE
Single-Chip Electronic Volume Control System
Overview
The LC75396NE is an electronic volume control system providing control over volume, balance, 5-band equalizer, and input switching based on serial inputs.
Package Dimensions
unit: mm 3159-QFP64E
[LC75396NE]
Functions
* Volume control: The chip provides 81 levels of volume attenuation: in 1dB step between 0 dB and -79 dB and -. Independent control over left front/rear and right front/rear channels provides balance control. * Equalizer: The chip provides control in 2-dB steps over the range between +10 dB and -10 dB. Four of the five bands have peaking equalization; the remaining one, shelving equalization. * Selector: The left and right channels each offer a choice of five inputs. The L5 and R5 inputs can be turned on and off independently. An external constant determines the amplification for the input signal. * Serial data input -- Supports CCB* format communication with the system controller.
SANYO: QFP64E
Features
* Built-in buffer amplifiers reduce the number of external parts required. * Silicon gate CMOS process reduces the noise of built-in switch. * VDD/2 reference voltage generation circuit built in.
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD CL, DI, CE, L1 to L5, R1 to R5, LTIN, RTIN, LFIN, RFIN, LRIN, RRIN Ta 75C, with PC board Conditions Ratings 11 VSS - 0.3 to VDD + 0.3 550 -30 to +75 -40 to +125 Unit V V mW C C
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TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
50698RM (OT) No. 5914-1/19
LC75396NE Allowable Operating Ranges at Ta = - 30 to + 75C, VSS = 0 V
Parameter Supply voltage Input high level voltage Input low level voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN toW tSETUP tHOLD fopg VDD CL, DI, CE CL, DI, CE CL, DI, CE, L1 to L5, R1 to R5, LTIN, RTIN, LFIN, RFIN, LRIN, RRIN CL CL, DI, CE CL, DI, CE CL Conditions Ratings min 6.0 4.0 VSS VSS 1.0 1.0 1.0 500 typ max 10.5 VDD 1.0 VDD Unit V V V Vp-p s s s kHz
Electrical Characteristics at Ta = 25C, VDD = 10 V, VSS = 0 V
Parameter [Input block] Input resistance Clipping level Output load resistance [Volume control block] Input resistance [Equalizer control block] Control range Step resolution Internal feedback resistance [Overall characteristics] Total harmonic distortion Crosstalk Output noise voltage Output at maximum attenuation Current drain Input high level current Input low level current THD CT VN 1 VN 2 VO min IDD IIH IIL VIN = 1 Vrms, f = 1 kHz, with all controls flat overall VIN = 1 Vrms, f = 1 kHz, with all controls flat overall, Rg = 1 k With all controls flat overall, BW = 20 to 20kHz GEQ F1 Band = +10dB, With all controls overall, BW = 20 to 20kHz VIN = 1 Vrms, f = 1 kHz, main volume - VDD - VSS = 10.5 V CL, DI, CE, VIN = 10.5 V CL, DI, CE, VIN = 0 V -10 80 2.9 17 -90 46.5 55.8 10 0.01 % dB V V dB mA A A Geq Estep Rfeed Max, boost/cut 8 1 17 10 2 28 12 3 39 dB dB k Rin LFIN, LRIN, RFIN, RRIN 100 k Rin Vcl RL L1 to L5, R1 to R5 LSELO, RSELO: THD = 1.0% LSELO, RSELO 10 50 3.00 k Vrms k Symbol Conditions Ratings min typ max Unit
No. 5914-2/19
LC75396NE Sample Application Circuit
No. 5914-3/19
LC75396NE Test Circuits Total Harmonic Distortion
No. 5914-4/19
LC75396NE Output Noise Voltage
No. 5914-5/19
LC75396NE Crosstalk
No. 5914-6/19
LC75396NE Pin Assignment
No. 5914-7/19
LC75396NE Pin Functions
Pin No. 55 54 53 52 51 57 58 59 60 61 Pin L1 L2 L3 L4 L5 R1 R2 R3 R4 R5 Signal inputs Function Equivalent circuit
50 62
LINVIN1 RINVIN1
Inverting inputs to the operational amplifier that sets the input gain
49 63
LSELO RSELO
Input selector outputs
48 64
LTIN RTIN
Equalizer inputs
47 46 45 1 2 3 44 43 42 4 5 6 41 40 39 7 8 9 38 37 36 10 11 12
LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 LF2C1 LF2C2 LF2C3 RF2C1 RF2C2 RF2C3 LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3 LF4C1 LF4C2 LF4C3 RF4C1 RF4C2 RF4C3 * Connections for the capacitors that form the equalizer F4 band filters Capacitors must be connected between: LF4C1 (RF4C1) and LF4C2 (RF4C2), and between LF4C2 (RF4C2) and LF4C3 (RF4C3). * Connections for the capacitors that form the equalizer F3 band filters Capacitors must be connected between: LF3C1 (RF3C1) and LF3C2 (RF3C2), and between LF3C2 (RF3C2) and LF3C3 (RF3C3). * Connections for the capacitors that form the equalizer F2 band filters Capacitors must be connected between: LF2C1 (RF2C1) and LF2C2 (RF2C2), and between LF2C2 (RF2C2) and LF2C3 (RF2C3). * Connections for the capacitors that form the equalizer F1 band filters Capacitors must be connected between: LF1C1 (RF1C1) and LF1C2 (RF1C2), and between LF1C2 (RF1C2) and LF1C3 (RF1C3).
Continued on next page.
No. 5914-8/19
LC75396NE
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
35 13
LF5 RF5
* Connections for the capacitors that form the equalizer F5 band filters Connections for external capacitors
33 30 15 18
LFIN LRIN RFIN RRIN
* Input to the left channel front 4-dB step volume control. * Input to the left channel rear 4-dB step volume control. * Input to the right channel front 4-dB step volume control. * Input to the right channel rear 4-dB step volume control.
32 29 16 19
LFCOM LRCOM RFCOM RRCOM
* Common pin for the left channel front 1-dB step volume control. * Common pin for the left channel rear 1-dB step volume control. * Common pin for the right channel front 1-dB step volume control. * Common pin for the right channel rear 1-dB step volume control.
31 28 17 20
LFOUT LROUT RFOUT RROUT
* Left channel front volume control output * Left channel rear volume control output * Right channel front volume control output * Right channel rear volume control output
34 14
LTOUT RTOUT
* Equalizer outputs
22
Vref
* A capacitor of a few tens of F must be inserted between Vref and AVSS (VSS) to handle power supply ripple in the VDD/2 voltage generation circuit.
27 21
LVref RVref
* Internal analog system grounds
56 26
VDD VSS
* Power supply * Ground
* Chip enable 25 CE When this pin goes from high to low, data is written to an internal latch and the analog switches operate. Data transfers are enabled when this pin is at the high level.
24 23
DI CL
* Serial data and clock inputs for chip control.
No. 5914-9/19
LC75396NE Equivalent Circuit Diagram Selector Control Block
Equalizer Control Block
No. 5914-10/19
LC75396NE Volume Control Block
Calculating the Size of External Capacitors The LC75396NE supports four bands with peaking characteristics and one band with shelving characteristics 1. Peaking Characteristics (bands F1 to F4) The external capacitor functions as the structural element of a simulated inductor. The equivalent circuit and the calculations required to achieve the desired center frequency are shown below. * Equivalent circuit for the simulated inductor
Zo: Impedance at resonance
No. 5914-11/19
LC75396NE * Calculation example Specifications: Central frequency, FO = 107 Hz Q factor at maximum boost, Q+10 dB = 0.8 -- Calculate QO, the sharpness of the simulated inductance itself. QO = (R1 + R4)/R1 x Q+10dB Note: R4 is from the separately issued internal block diagram. 4.270 -- Calculate C1 C1 = 1/2FOR1QO 0.536 (F) -- Calculate C2 C2 = QO/2FOR2 0.021 (F) * Sample results
Central frequency FO (Hz) 107 340 1070 3400 C1 (F) 0.536 0.169 0.054 0.017 C2 (F) 0.021 6663 P 2117 P 666 P
2. Shelving characteristics (Band F5) Achieving the desired control of 2-dB steps over the range between +10 dB to -10 dB requires choosing a capacitor, C3, with an impedance of 650 .
Control System Timing and Data Formats To control the LC75396NE, specified sequences are required to be input through the pins CE, CL, and DI. Each sequence consists of 48 bits: an 8-bit address followed by 40 bits of data.
No. 5914-12/19
LC75396NE 1. Address Code (B0 to A3) This product uses an 8-bit address code, and supports the same specifications as other Sanyo CCB serial bus products. Address code (LSB)
2. Control Code Allocations Input switching control
Operation
Input switching control
Operation
Five band equalizer control
Band f1 Band f2 Band f3 Band f4 Band f5
No. 5914-13/19
LC75396NE Volume control
Operation
Channel selection control
Operation Initial setting
Simulataneous left and right
Left channel volume rear/front control
Operation Rear Front
Control is enabled when D33 = 1
Right channel volume rear/front control
Operation Rear Front
Control is enabled when D32 = 1
Test mode control
Operation These bits are for chip testing and must all be set to 0 in application systems.
Notes:
After power is first applied, applications must initialize this chip by sending the initial data (1) and (2) described below. Initial data ... (1) Address 01000001 Data: (Set the volume to -set both D34 and D35 to 1, and set all other data to 0) (2) Address 01000001 Data: (Set the volume to -, set both D34 and D35 to 0, and set all other data to 0) After transferring that data, set the left and right channel initial settings before turning off the mute function.
No. 5914-14/19
LC75396NE
fO ( Center Frequency) Characteristics
Volume Step Characteristics
THD - Frequency Characteristics (1)
Flat overall When step = - Front and rear volume set to -
80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat
No. 5914-15/19
LC75396NE
THD - Frequency Characteristics (2) THD - Frequency Characteristics (3)
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position
All bands boosted All bands cut
Volume: -10 dB position
Volume: 0 dB position
Flat
Frequency, f -- Hz
Frequency, f -- Hz
THD - Supply Voltage Characteristics (1)
THD - Supply Voltage Characteristics (1)
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat
80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat
Volume: -10
dB position
Volume: -10 dB position
Volume: 0 dB position
Volume
: 0 dB
positio
n
Supply voltage, VDD -- V
Supply voltage, VDD -- V
No. 5914-16/19
LC75396NE
THD - Supply Voltage Characteristics (3) THD - Input Level Characteristics (1)
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position
All bands boos ted
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Graphic equalizer: flat
All bands cut
Flat
Supply voltage, VDD -- V
Input level, VIN -- dBV
THD - Input Level Characteristics (2)
THD - Input Level Characteristics (3)
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: -10 dB position Graphic equalizer: flat
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position
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Input level, VIN -- dBV
Input level, VIN -- dBV
No. 5914-17/19
LC75396NE
THD - Output Level Characteristics (1) THD - Output Level Characteristics (2)
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Graphic equalizer: flat
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: -10 dB position Graphic equalizer: flat
Outut level, VO -- dBV
Outut level, VO -- dBV
THD - Output Level Characteristics (3)
Total harmonic distortion, THD -- %
80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position
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Outut level, VIN -- dBV
Usage Notes * When the power is first applied, the internal analog switches are in indeterminate states. The chip therefore requires muting or other external measures until it has received the proper data. * After power is first applied, applications must initialize this chip by sending the initial data (1) and (2) described below. Initial data ... (1) Address 01000001 Data: (Set the volume to -, set both D34 and D35 to 0, and set all other data to 0) (2) Address 01000001 Data: (Set the volume to -, set both D34 and D35 to 1, and set all other data to 0) After transferring that data, set the left and right channel initial settings before turning off the mute function. * Provide grounding patterns or shielding for the lines to the CL, DI, and CE pins so as to prevent their high-frequency digital signals from interfering with the operation of nearby analog circuits.
No. 5914-18/19
LC75396NE
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. No. 5914-19/19

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